CoBo PCB is a custom Advanced Mezzanine Card (AMC) 14-layer board designed at NSCL. It utilizes Xilinx Virtex-5 System-on-chip (XC5VFX100T-1FFG1136C) which contains a relatively large FPGA as well as dual PowerPC 440 CPU cores.

The PCB conforms with MicroTCA.0 R1.0 PICMG double-width full-height standard. Please refer to “PICMG Specifications MTCA.0 R1.0 Micro Telecommunications Computing Architecture Base Specification July 6, 2006”. See short form

Main hardware components:

• Xilinx Virtex-5 XC5VFX100T-1FF1136C

• Two Dual-VHDCI Stacked Connectors. Molex 74337-0054
• 170-Pin AMC plug backplane connector for µTCA. Harting 16231701301000
• Two Dual-LEMOs IO. LEMO EPY.00.250.NTN.
  • IOs are buffered through Maxim MAX3378EEUD+.
  • IO voltage is settable to 3.3v or 5.0v using jumper JP8.
• USB-to-UARL, TE Conn. 1981584-1
  • compatible cable Molex 0687840001
  • conversion is done using SiLabs CP2102-GM

• 256MB DDR2 SDRAM. Micron MT47H64M16HR-3:H TR
• 128MB Parallel Flash. Micron PC28F128P30TF65A

• USB-RS232 Port, Micro USB
• 1GbE and 10GbE on the µTCA backplane connector using Virtex-5 GTX
• Slow/Fast Control AsAD

• External 12V supply through Molex 0015244449 or µTCA backplane connector.
• 3 Switching regulators: 5V, 3.3V, and 1.0V.
• 6 Linear regulators: three 0.9V, two 1.0V, one 1.2V, and one 2.5V. Derived from Switching regulators above.

• Xilinx Parallel Cable IV or Platform USB Cable support for JTAG Programming/Configuration using header (J3).
• Using BPI Flashing using switch (S2).
• Using MicroTCA backplane JTAG connection

The configuration mode is selected by setting shunts (jumpers) the dedicated Mode input pins M[2:0]. The mode pins should not be toggled during and after configuration.

Front Panel
CoBo Design
CoBo Implementation
CoBo Testing

This page is under construction