CoBo Printed Circuit Board

CoBo PCB is a custom Advanced Mezzanine Card (AMC) 14-layer board designed at NSCL. It utilizes Xilinx Virtex-5 System-on-chip (XC5VFX100T-1FFG1136C) which contains a relatively large FPGA as well as dual PowerPC 440 CPU cores.

The PCB conforms with MicroTCA.0 R1.0 PICMG double-width full-height standard. Please refer to “PICMG Specifications MTCA.0 R1.0 Micro Telecommunications Computing Architecture Base Specification July 6, 2006”. See short form

Main hardware components:

• Xilinx Virtex-5 XC5VFX100T-1FF1136C

• Two Dual-VHDCI Stacked Connectors. Molex 74337-0054
• 170-Pin AMC plug backplane connector for µTCA. Harting 16231701301000
• Two Dual-LEMOs IO. LEMO EPY.00.250.NTN.
  • IOs are buffered through Maxim MAX3378EEUD+.
  • IO voltage is settable to 3.3v or 5.0v using jumper JP8.
• USB-to-UARL, TE Conn. 1981584-1
  • compatible cable Molex 0687840001
  • conversion is done using SiLabs CP2102-GM

• 256MB DDR2 SDRAM. Micron MT47H64M16HR-3:H TR

  • CORE Generator Options:
       Target Device                  : xc5vfx70t-ff1136
       Speed Grade                    : -1
       HDL                            : vhdl
       Synthesis Tool                 : ISE
    
    MIG Output Options:
       Module Name                    : mig_36_1
       No of Controllers              : 1
       Selected Compatible Device(s)  : xc5vfx100t-ff1136
       Hardware Test Bench           : disabled
       PPC440                         : enabled
       PowerPC440 Block Selection     : Top
    
    FPGA Options:
       PLL                            : enabled
       Debug Signals                  : Disable
       System Clock                   : Differential
       Limit to 2 Bytes per Bank      : disabled
    
    Extended FPGA Options:
       DCI for DQ/DQS                 : disabled
       DCI for Address/Control        : disabled
       Class for Address and Control  : Class II
    
    Reserve Pins:
       --
        
       /*******************************************************/
       /*                  Controller 0                       */
       /*******************************************************/
       Controller Options :
          Memory                         : DDR2_SDRAM
          Design Clock Frequency         : 5000 ps(200.00 MHz)
          Memory Type                    : Components
          Memory Part                    : MT47H64M16XX-3
          Equivalent Part(s)             : MT47H64M16HR-3;MT47H64M16BT-3
          Data Width                     : 32
          Memory Depth                   : 1
          ECC                            : ECC Disabled
          Data Mask                      : enabled
    
       Memory Options:
          Burst Length (MR[2:0])         : 4(010)
          Burst Type (MR[3])             : sequential(0)
          CAS Latency (MR[6:4])          : 4(100)
          Output Drive Strength (EMR[1]) : Fullstrength(0)
          RTT (nominal) - ODT (EMR[6,2]) : 75ohms(01)
          Additive Latency (EMR[5:3])    : 0(000)
    
       FPGA Options:
          IODELAY Performance Mode       : HIGH
    
       Selected Banks and Pins usage : 
           Data          :bank 11
                          bank 13
                          
           Address/Control:bank 11
                          bank 13
                          bank 17
                          
           System Control:bank 17
                          
           System Clock  :bank 4
                          

• 32MB Parallel Flash. Micron PC28F256P30TFE
  • For BPI booting paging has been enabled in CoBo's firmware

    • -g ConfigRate:17
      -g BPI_page_size:8
      -g BPI_1st_read_cycle:4 

    • The flash is divided to three blocks

• USB-RS232 Port, Micro USB
• 1GbE and 10GbE on the µTCA backplane connector using Virtex-5 GTX
• Slow/Fast Control AsAD
• Double Data Rate CoBo-Mutant link

• External 12V µTCA backplane power or using Molex 39890-0302 (for bench testing)
• 3 Switching regulators: 5V, 3.3V, and 1.0V.
• 6 Linear regulators

• Xilinx Parallel Cable IV or Platform USB Cable support for JTAG Programming/Configuration using header (J4).
• Using BPI Flash.
• Using MicroTCA backplane JTAG connection

The configuration mode is selected by setting shunts (jumpers) the dedicated Mode input pins M[2:0] on (JP11). The mode pins should not be toggled during and after configuration.

Front Panel
CoBo Design
CoBo Implementation
CoBo Testing

This page is under construction