This shows you the differences between two versions of the page.
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asics:setup_guide [2010/09/10 17:09] dancoupland created, copying text from old pdf. Should check for updates and include images later. |
asics:setup_guide [2010/09/14 12:16] (current) dancoupland Added a couple of the figures |
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| * All rack crates are connected to clean ground power. | * All rack crates are connected to clean ground power. | ||
| * The spdaq computer is connected to dirty power. | * The spdaq computer is connected to dirty power. | ||
| - | - Connect electronic cables between tower and flange(s), and then from flange(s) to rack (see Figure 1.) | + | - Connect electronic cables between tower and flange(s), and then from flange(s) to rack (see Figure 1.){{ : |
| * Use cables intended to be used inside a vacuum chamber. These will often be shielded from electronic noise using a metallic foil and insulated with a nylon sleeving. | * Use cables intended to be used inside a vacuum chamber. These will often be shielded from electronic noise using a metallic foil and insulated with a nylon sleeving. | ||
| * The thermocouple output is a 34-pin cable, but in the digital voltmeter accepts lemo connections. | * The thermocouple output is a 34-pin cable, but in the digital voltmeter accepts lemo connections. | ||
| * Make sure the thermocouple box is also isolated from the chamber. | * Make sure the thermocouple box is also isolated from the chamber. | ||
| * Ground the cables to the tower, flange, or rack, usually with alligator clips. | * Ground the cables to the tower, flange, or rack, usually with alligator clips. | ||
| - | - Wire up the modules in the rack (see Figure 2.) | + | - Wire up the modules in the rack (see Figure 2.){{ : |
| * The XLM ECL connection is configured so that the first 8 signals are inputs to the XLM and the second 8 are outputs. | * The XLM ECL connection is configured so that the first 8 signals are inputs to the XLM and the second 8 are outputs. | ||
| * Pin assignments on the inspect channels and XLM ECL connection are listed in Table 2 and 3. | * Pin assignments on the inspect channels and XLM ECL connection are listed in Table 2 and 3. | ||
| * A detailed explanation for the wiring follows in the next section. | * A detailed explanation for the wiring follows in the next section. | ||
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| ====Introduction to HiRA acquisition logic / explanation of wiring==== | ====Introduction to HiRA acquisition logic / explanation of wiring==== | ||