Differences between CoBo 1.0v and CoBo 0.2v

Rocket IO GTX Transceiver improvements
- Bank 12 is no longer used. All (3V3) signals on that bank have been moved to bank 20
  - Now banks 12, 15, and 22 are not used
- Re-routed signals away from MGT VCC/GND
Improved board power and power management
- VCCINT, VCC3V3, and VCC5V0 no longer require a 350Khz resonator. i.e. Sync is disabled
- VCCINT now uses a 10A switching regulator instead of a 16A
- Input capacitance now conforms with MicroTCA requirement. i.e. it doesn't exceed 800uF
  - (C113) and (C122) are now 220uF instead of 330uF
- Improved Power up sequence
  - No longer uses an additional (U35) chip (TPS3808G09DBVR)
  - Power-up sequence used to be VCCINT → VCC3V3 & VCC5V0. Now it is VCC5V0 → VCC3V3 → VCCINT
    - This reduces a race condition when BPI booting from flash
    - DDR2 memory is powered up after VCC5V0 turns on
    - VCC3V3 Auto Track pin is connected to VCC5V0. VCCINT Auto Track pin is connected to VCC3V3
Mutant WSCA/SYNC signal is now on a CC pin
Footprint updates
- (U36), (U38), and (U39) Switching regulators have updated hole sizes for better fitting
- (SW2) HDT001 switch layout fixes
Changed Clocking (see CoBo Clocking)
- CKRs traces from PLL to LVDS buffer and from LVDS buffer to VHDCI connector are now equal
- CKWs traces from PLL to LVDS buffer and from LVDS buffer to VHDCI connector are now equal
- On LMK04800 (U41) CLKin1 no longer uses MCH clock as an input. A dedicated oscillator is now used (X9)
- re-arranged outputs on LMK04800 (U41)
Consistent labeling and naming scheme on Front panel
Move usb-uart (J3) foward i.e. closer to front panel
USB-UART (U60) is power thru USB
Add 0 ohm resistors between MAX3378EEUD+ and FPGA (LEMO)
Radianheatsinks INH35001-18/2.6K29+T710 is now used for Virtex-5