Differences

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--- cobo_pcb [2014/05/23 14:26] – abunimeh
+++ cobo_pcb [2014/05/23 15:01] (current) – [Memory] abunimeh
@@ Line 21: / Line 21: @@
 ==== Memory ====
   * 256MB DDR2 SDRAM. [[http://www.micron.com/parts/dram/ddr2-sdram/mt47h64m16hr-3-it|Micron MT47H64M16HR-3:H TR]]
-  * 32MB Parallel Flash. [[http://www.micron.com/parts/nor-flash/parallel-nor-flash/pc28f256p30tfe|Micron PC28F256P30TFE]]
+    * <code>
+CORE Generator Options:
+   Target Device                  : xc5vfx70t-ff1136
+   Speed Grade                    : -1
+   HDL                            : vhdl
+   Synthesis Tool                 : ISE
+MIG Output Options:
+   Module Name                    : mig_36_1
+   No of Controllers              : 1
+   Selected Compatible Device(s)  : xc5vfx100t-ff1136
+   Hardware Test Bench           : disabled
+   PPC440                         : enabled
+   PowerPC440 Block Selection     : Top
+FPGA Options:
+   PLL                            : enabled
+   Debug Signals                  : Disable
+   System Clock                   : Differential
+   Limit to 2 Bytes per Bank      : disabled
+Extended FPGA Options:
+   DCI for DQ/DQS                 : disabled
+   DCI for Address/Control        : disabled
+   Class for Address and Control  : Class II
+Reserve Pins:
+   --
+   /*******************************************************/
+   /*                  Controller 0                       */
+   /*******************************************************/
+   Controller Options :
+      Memory                         : DDR2_SDRAM
+      Design Clock Frequency         : 5000 ps(200.00 MHz)
+      Memory Type                    : Components
+      Memory Part                    : MT47H64M16XX-3
+      Equivalent Part(s)             : MT47H64M16HR-3;MT47H64M16BT-3
+      Data Width                     : 32
+      Memory Depth                   : 1
+      ECC                            : ECC Disabled
+      Data Mask                      : enabled
+   Memory Options:
+      Burst Length (MR[2:0])         : 4(010)
+      Burst Type (MR[3])             : sequential(0)
+      CAS Latency (MR[6:4])          : 4(100)
+      Output Drive Strength (EMR[1]) : Fullstrength(0)
+      RTT (nominal) - ODT (EMR[6,2]) : 75ohms(01)
+      Additive Latency (EMR[5:3])    : 0(000)
+   FPGA Options:
+      IODELAY Performance Mode       : HIGH
+   Selected Banks and Pins usage :
+       Data          :bank 11
+                      bank 13
+       Address/Control:bank 11
+                      bank 13
+                      bank 17
+       System Control:bank 17
+       System Clock  :bank 4
+</code>
+  * 32MB Parallel Flash. [[http://www.micron.com/parts/nor-flash/parallel-nor-flash/pc28f256p30tfe|Micron PC28F256P30TFE]]
+    * For BPI booting paging has been enabled in CoBo's firmware
+      * <code>-g ConfigRate:17
+-g BPI_page_size:8
+-g BPI_1st_read_cycle:4
+</code>
+      * The flash is divided to three blocks
+      *
 ==== Communication ====
   * USB-RS232 Port, Micro USB
@@ Line 31: / Line 105: @@
   * External 12V µTCA backplane power or using [[http://www.molex.com/molex/products/datasheet.jsp?part=active/0398900302_TERMINAL_BLOCKS.xml|Molex 39890-0302]] (for bench testing)
   * 3 Switching regulators: 5V,  3.3V, and 1.0V.
-  * 6 Linear regulators: three 0.9V, two 1.0V, one 1.2V, and one 2.5V. Derived from Switching regulators above.
+  * 6 Linear regulators
 ==== Configuration ====
   * Xilinx Parallel Cable IV or Platform USB Cable support for JTAG Programming/Configuration using header (J4).
   * Using BPI Flash.
   * Using MicroTCA backplane JTAG connection
-The configuration mode is selected by setting shunts (jumpers) the dedicated Mode input pins M[2:0]. The mode pins should not be toggled during and after configuration.
+The configuration mode is selected by setting shunts (jumpers) the dedicated Mode input pins M[2:0] on (JP11). The mode pins should not be toggled during and after configuration.