Differences

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--- cobo_clocking [2014/05/22 09:15] – abunimeh
+++ cobo_clocking [2014/05/23 14:18] (current) – [CKR and CKW] abunimeh
@@ Line 3: / Line 3: @@
 CoBo uses TI's [[http://www.ti.com/product/lmk04803|LMK04800]] family of Low-Noise Clock Jitter Cleaner with Dual Loop PLLs. In Cobo 0.2v and CoBo 1.0v LMK04803B is used. The internal VCO of the PLL is designed to run at 2 GHz in our application.
-CoBo LMK04803B PLL is responsible for receivering the Global Master Clock (GMC) from Mutant via the MicroTCA backplane on CLK3. After receiving the "dirty" GMC clock the LMK04803B attempts to clean the jitter and lock the PLL in order to generate multiple clocks.
+CoBo LMK04803B PLL is responsible for receivering the Global Master Clock (GMC) from Mutant via the MicroTCA backplane on CLK3. After receiving the "dirty" GMC clock the LMK04803B attempts to clean the jitter and lock the PLL1&PLL2 in order to generate multiple clocks.
 {{ :cobo1.0_clocking.png?500 |}}
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 There are two clock inputs and 12 outputs for CoBo's LMK04803B. The 1st input is CLKin0 which is connected to the GMC clock. There is some feedback logic that sits in between the LMK04803B and Mutants GMC buffer. The additive jitter of that logic is described [[gmc_jitter|here]]. The 2nd input is CLKin1, in CoBo 0.2v this is connected to MCH clock. However, in CoBo 1.0v a backup local oscillator is used instead. Therefore, by using CLKin1 with a local oscillator, it is possible for CoBo 1.0v to use the local 100MHz clock as a back up clock in case GMC doesn't exist or if you want to run CoBo in standalone mode.
-The 12 clock outputs are CKWs and CKRs for Asads and CoBo's FPGA (10 clocks), a buffered version of the VXCO clock, and a programmable clock.
+The 12 clock outputs are CKWs and CKRs (passed to Asads and FPGA -- total 10 clocks), a buffered version of the VXCO clock, and a programmable clock.
 CLKout0 = Asad1 CKR \\
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 ===== CKR and CKW =====
-CKR and CKW are AGET chip Read and Write clocks. These clocks are passed from LMK04803B to an LVDS buffer on CoBo and sent over VHDCI cables to Asads. We have tested the communication with a 10 meter VHDCI cable with CKW running at 100MHz. The table below lists the trace lengths on the PCB. AS* are the signals from the LMK04803B to the LVDS buffer, CK* (shorter traces) are the signals from the LVDS buffer to the VHDCI connector.
+CKR and CKW are AGET chip Read and Write clocks. These clocks are passed from LMK04803B to an LVDS buffer on CoBo and sent over VHDCI cables to Asads. We have tested the communication with a 10 meter VHDCI cable with CKW running at 100MHz (For longer cables consider setting JP9 to 1-2). The table below lists the trace lengths on the PCB. AS* are the signals from the LMK04803B to the LVDS buffer, CK* (shorter traces) are the signals from the LVDS buffer to the VHDCI connector.
+{{ ::ck_buffers.png?500 |}}
 ^Name		^Node Count		^Routed (mil) ^^
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 ====== Synchronization ======
-To synchronize the LMK04803B clocks on a single CoBo board, one has to send a pulse (positive pulse, see datasheet for the minimum length of this pulse) from the FPGA to the LMK04803B chip using //PLL_SYNC// signal on pin F8. The length of the PCB trace is 1320.475 mils.
+To synchronize the LMK04803B clocks on a single CoBo board, one has to send a pulse (at least 0.5ns positive pulse, see datasheet for the minimum length of this pulse and polarity) from the FPGA to the LMK04803B chip using //PLL_SYNC// signal on pin F8. The length of the PCB trace is 1320.475 mils.
 The default configuration requires the Mutant and the CoBo to calibrate the GMC/WSCA links between them first. After that the Mutant sends a SYNC command to all CoBos on the WSCA line. CoBo uses that command to sync its own clocks.