Differences

This shows you the differences between two versions of the page.

--- cobo_clocking [2014/05/19 16:26] – abunimeh
+++ cobo_clocking [2014/05/23 14:18] (current) – [CKR and CKW] abunimeh
@@ Line 3: / Line 3: @@
 CoBo uses TI's [[http://www.ti.com/product/lmk04803|LMK04800]] family of Low-Noise Clock Jitter Cleaner with Dual Loop PLLs. In Cobo 0.2v and CoBo 1.0v LMK04803B is used. The internal VCO of the PLL is designed to run at 2 GHz in our application.
-CoBo LMK04803B PLL is responsible for receivering the Global Master Clock (GMC) from Mutant via the MicroTCA backplane on CLK3. After receiving the "dirty" GMC clock the LMK04803B attempts to clean the jitter and lock the clock in order to generate multiple clocks.
+CoBo LMK04803B PLL is responsible for receivering the Global Master Clock (GMC) from Mutant via the MicroTCA backplane on CLK3. After receiving the "dirty" GMC clock the LMK04803B attempts to clean the jitter and lock the PLL1&PLL2 in order to generate multiple clocks.
 {{ :cobo1.0_clocking.png?500 |}}
@@ Line 9: / Line 9: @@
 There are two clock inputs and 12 outputs for CoBo's LMK04803B. The 1st input is CLKin0 which is connected to the GMC clock. There is some feedback logic that sits in between the LMK04803B and Mutants GMC buffer. The additive jitter of that logic is described [[gmc_jitter|here]]. The 2nd input is CLKin1, in CoBo 0.2v this is connected to MCH clock. However, in CoBo 1.0v a backup local oscillator is used instead. Therefore, by using CLKin1 with a local oscillator, it is possible for CoBo 1.0v to use the local 100MHz clock as a back up clock in case GMC doesn't exist or if you want to run CoBo in standalone mode.
-The 12 clock outputs are CKWs and CKRs for Asads and CoBo's FPGA (10 clocks), a buffered version of the VXCO clock, and a programmable clock.
+The 12 clock outputs are CKWs and CKRs (passed to Asads and FPGA -- total 10 clocks), a buffered version of the VXCO clock, and a programmable clock.
-CLKout0 = Asad1 CKR
+CLKout0 = Asad1 CKR \\
-CLKout1 = Asad0 CKR (settings are tied with CLKout0)
+CLKout1 = Asad0 CKR (settings are tied with CLKout0)\\
-CLKout2 = Asad3 CKR
+CLKout2 = Asad3 CKR\\
-CLKout3 = Asads CKR (settings are tied with CLKout2)
+CLKout3 = Asads CKR (settings are tied with CLKout2)\\
-CLKout4 = FPGA CKR
+CLKout4 = FPGA CKR\\
-CLKout5 = FPGA PLL CLK (for testing or driving any logic inside of FPGA at 25MHz) (settings are tied with CLKout4)
+CLKout5 = FPGA PLL CLK (for testing or driving any logic inside of FPGA at 25MHz) (settings are tied with CLKout4)\\
-CLKout6 = Asad1 CKW
+CLKout6 = Asad1 CKW\\
-CLKout7 = Asad0 CKW (settings are tied with CLKout6)
+CLKout7 = Asad0 CKW (settings are tied with CLKout6)\\
-CLKout8 = Asad3 CKW
+CLKout8 = Asad3 CKW \\
-CLKout9 = Asad2 CKW (settings are tied with CLKout8)
+CLKout9 = Asad2 CKW (settings are tied with CLKout8)\\
-CLKout10 = FPGA CKW (settings are tied with CLKout11 -- not connected on PCB)
+CLKout10 = FPGA CKW (settings are tied with CLKout11 -- not connected on PCB)\\
-OscOut0 = FPGA buffer VXCO
+OscOut0 = FPGA buffer VXCO\\
 ===== CKR and CKW =====
-CKR and CKW are AGET chip Read and Write clocks. These clocks are passed from LMK04803B to an LVDS buffer on CoBo and sent over VHDCI cables to Asads. We have tested the communication with a 10 meter VHDCI cable with CKW running at 100MHz. The table below lists the trace lengths on the PCB. AS* are the signals from the LMK04803B to the LVDS buffer, CK* (shorter traces) are the signals from the LVDS buffer to the VHDCI connector.
+CKR and CKW are AGET chip Read and Write clocks. These clocks are passed from LMK04803B to an LVDS buffer on CoBo and sent over VHDCI cables to Asads. We have tested the communication with a 10 meter VHDCI cable with CKW running at 100MHz (For longer cables consider setting JP9 to 1-2). The table below lists the trace lengths on the PCB. AS* are the signals from the LMK04803B to the LVDS buffer, CK* (shorter traces) are the signals from the LVDS buffer to the VHDCI connector.
+{{ ::ck_buffers.png?500 |}}
 ^Name		^Node Count		^Routed (mil) ^^
@@ Line 67: / Line 69: @@
 ====== Synchronization ======
-To synchronize the LMK04803B clocks on a single CoBo board, one has to send a pulse (positive pulse, see datasheet for the minimum length of this pulse) from the FPGA to the LMK04803B chip using //PLL_SYNC// signal on pin F8. The length of the PCB trace is 1320.475 mils.
+To synchronize the LMK04803B clocks on a single CoBo board, one has to send a pulse (at least 0.5ns positive pulse, see datasheet for the minimum length of this pulse and polarity) from the FPGA to the LMK04803B chip using //PLL_SYNC// signal on pin F8. The length of the PCB trace is 1320.475 mils.
 The default configuration requires the Mutant and the CoBo to calibrate the GMC/WSCA links between them first. After that the Mutant sends a SYNC command to all CoBos on the WSCA line. CoBo uses that command to sync its own clocks.
@@ Line 162: / Line 164: @@
   * For syncing you can either do the LEMO method or the SYNC_EN_AUTO method
+Below is an ecc script example of CoBo 0.2v running PLL2 only. The SYNC polarity must be inverted if Mutant is plugged in (regardless of GMC being supplied or not)
+<code>
+connect node 192.168.40.50
+load hardwareDescription_fullCoBoStandAlone.xcfg
+connect device pll
+pll-reset
+pll-write 0x00020000
+pll-write 0x00000A00
+pll-write 0x00000A01
+pll-write 0x00000A02
+pll-write 0x00000A03
+pll-write 0x00000A04
+pll-write 0x00000A05
+pll-write 0x11110006
+pll-write 0x11110007
+pll-write 0x01110008
+pll-write 0x55555549
+pll-write 0x9140400A
+pll-write 0x3401A00B
+pll-write 0x0B0C006C
+pll-write 0x1B12902D
+pll-write 0x1200000E
+pll-write 0x8000800F
+pll-write 0x01550410
+pll-write 0x000000D8
+pll-write 0x01010019
+pll-write 0xAFA8001A
+pll-write 0x1C0000DB
+pll-write 0x002000DC
+pll-write 0x0180015D
+pll-write 0x0200015E
+pll-write 0x001F001F
+</code>