S800 Documentation

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trigger [2023/10/24 16:47]
swartzj [Trigger schematics] 		trigger [2024/09/25 13:14] (current)
pereira [Time stamping]
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 ^         |                   ^ B16 (out) | Time stamp clock      ^ C16 (out) |                  ^ D16 (out) | 1 Hz | ^         |                   ^ B16 (out) | Time stamp clock      ^ C16 (out) |                  ^ D16 (out) | 1 Hz |
 ==== FPGA firmware ==== ==== FPGA firmware ====
-The firmware of the trigger module is shown in the following files. The {{:wiki:Usbtrig.pdf|PDF file}} contains the schematic sheets, used for most of the design. The [[Verilog Trigger|Verilog file]] contains the block dealing with CAMAC communications.+Schematics of the firmware exist in S800 document folders (contact [[pereira@frib.msu.edu]]).
  
  
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 The S800 ULM trigger module provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used (as it is done, for instance, when running with GRETINA). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section "[[Trigger#Begin sequence|Begin sequence]]"). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized.  The S800 ULM trigger module provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used (as it is done, for instance, when running with GRETINA). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section "[[Trigger#Begin sequence|Begin sequence]]"). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized. 
  
-The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate (or in other data acquisition systems coupled to the S800). The S800 VME time-stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available {{:wiki:stamp64.pdf|here}}. The inputs are the following: +The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate (or in other data acquisition systems coupled to the S800). The S800 VME time-stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available in S800 document folders (contact [[pereira@frib.msu.edu]]). The inputs are the following: 
  
  
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 The clear can be done via software as well, and is usually done that way.  The clear can be done via software as well, and is usually done that way. 
  
-The [[Verilog Time stamping|Verilog file]] contains the code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME. 
  
  
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-====== Begin sequence ====== 
-OBSOLETE: THIS SECTION IS BEING UPDATED 
- 
-The internal "Go" state of the trigger module is controlled via CAMAC commands. When "Go" is false, the trigger and time stamp clock signals are vetoed and therefore absent. This way all time stamp counters can be safely zeroed during the beginning sequence of the data acquisition systems. The last command of the CAMAC beginning sequence sets the "Go" state to true, at which point both trigger and time stamp signals are released. This mechanism ensures that all time stamp counters are synchronized. 
- 
-The data acquisition begin sequence of the trigger module is the following: 
-  - reset time stamp counter to 0 
-  - reset trigger register to 0 
-  - after all modules in all crates have been initialized, send CAMAC command to set "Go" state to true 
-  - after a preset delay of 200 to 300 microseconds, the "Go" level is set to true 
-  
-The last step of the begin sequence allows enough time for the CC-USB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the "Go" state of the module back to false. 
  
 ====== Scalers and dead time ====== ====== Scalers and dead time ======
trigger.1698180446.txt.gz ยท Last modified: 2023/10/24 16:47 by swartzj

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