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--- trigger [2015/10/20 12:45]
pereira [Scalers and dead time]
+++ trigger [2024/09/25 13:14] (current)
pereira [Time stamping]
@@ Line 36: / Line 36: @@
 ===== Trigger schematics =====
-The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. The GUI is automatically displayed when clicking in the Readout icon of the [[software|u6pc5]] desktop.
+The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. The GUI is automatically displayed when clicking in the Readout icon of the [[software|u4pc8]] desktop.
 {{:wiki:TriggerGUI.png?900|Trigger schematics of the S800}}
@@ Line 56: / Line 56: @@
 ==== Inspect channels ====
-A set of four inspect channels are patched out to the data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit.
+A set of four inspect channels are patched out to the data-U4 panels. Each channel can be assigned to any connection drawn on the GUI by right clicking on the corresponding drawn "wire", thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit.
@@ Line 85: / Line 85: @@
 ^ A4 (in) | External 2 source ^ B4 (out)  | QDC gate              ^ C4 (in)   | Busy 4           ^ D4 (out)  | External 2 source |
 ^ A5 (in) | Clear busy        ^ B5 (out)  | TDC start             ^ C5 (in)   | Busy 5           ^ D5 (out)  | S800 trigger |
-^ A6 (in) | Clear module      ^ B6 (out)  | Trigger register gate ^ C6 (in)   | Busy 6           ^ D6 (out)  | Coincidence trigger |
+^ A6 (in) | Clear module      ^ B6 (out)  | Trigger register gate ^ C6 (in)   | Busy 6   ^ D6 (out)  | Coincidence trigger |
 ^ A7 (in) | Gretina sync      ^ B7 (out)  |                       ^ C7 (in)   | Busy 7           ^ D7 (out)  | External 1 trigger |
 ^ A8 (in) | Time stamp clock  ^ B8 (out)  | Live trigger          ^ C8 (in)   | Time stamp latch ^ D8 (out)  | External 2 trigger|
@@ Line 97: / Line 97: @@
 ^         |                   ^ B16 (out) | Time stamp clock      ^ C16 (out) |                  ^ D16 (out) | 1 Hz |
 ==== FPGA firmware ====
-The firmware of the trigger module is shown in the following files. The {{:wiki:Usbtrig.pdf|PDF file}} contains the schematic sheets, used for most of the design. The [[Verilog Trigger|Verilog file]] contains the block dealing with CAMAC communications.
+Schematics of the firmware exist in S800 document folders (contact [[pereira@frib.msu.edu]]).
 ====== Time stamping ======
-The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger#Trigger Schematics|GUI]]). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section "[[Trigger#Begin sequence|Begin sequence]]"). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized.
+The S800 ULM trigger module provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used (as it is done, for instance, when running with GRETINA). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section "[[Trigger#Begin sequence|Begin sequence]]"). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized.
-The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800.
+The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate (or in other data acquisition systems coupled to the S800). The S800 VME time-stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available in S800 document folders (contact [[pereira@frib.msu.edu]]). The inputs are the following:
-The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available {{:wiki:stamp64.pdf|here}}. The inputs are the following:
@@ Line 117: / Line 114: @@
 The clear can be done via software as well, and is usually done that way.
-The [[Verilog Time stamping|Verilog file]] contains the code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME.
@@ Line 124: / Line 120: @@
 ====== Configuration for S800 in tandem with other detectors ======
-In its standard configuration, the S800 data acquisition uses one CAMAC crate and one VME crate only. The CC-USB and VM-USB crate controller modules performing the readout are connected to the latches number 1 and 2 of the trigger module, respectively. Each crate controller is configured to output their busy and end-of-event signals on their available NIM outputs, which are then connected to the appropriate inputs on the trigger module.
+In its standard configuration, the S800 data acquisition uses one CAMAC crate and one VME crate only. The CC-USB and VM-USB crate controller modules performing the readout are connected to the latches number 1 and 2 ([[Trigger#Inputs and outputs|inputs C1 and C2]]) of the trigger module, respectively. Each crate controller is configured to output their busy and end-of-event signals on their available NIM outputs, which are then connected to the appropriate inputs on the trigger module.
 To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following:
@@ Line 158: / Line 154: @@
-====== Begin sequence ======
-The internal "Go" state of the trigger module is controlled via CAMAC commands. When "Go" is false, the trigger and time stamp clock signals are vetoed and therefore absent. This way all time stamp counters can be safely zeroed during the beginning sequence of the data acquisition systems. The last command of the CAMAC beginning sequence sets the "Go" state to true, at which point both trigger and time stamp signals are released. This mechanism ensures that all time stamp counters are synchronized.
-The data acquisition begin sequence of the trigger module is the following:
-  - reset time stamp counter to 0
-  - reset trigger register to 0
-  - after all modules in all crates have been initialized, send CAMAC command to set "Go" state to true
-  - after a preset delay of 200 to 300 microseconds, the "Go" level is set to true
-The last step of the begin sequence allows enough time for the CC-USB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the "Go" state of the module back to false.
 ====== Scalers and dead time ======
-The "D" connector of the trigger module is directly connected to 16 inputs of a scaler module (see mapping of the inputs and outputs of the trigger module in section [[Trigger#Inputs and outputs|Inputs and outputs]]). Scalers are connected to each of the trigger source inputs, as well as trigger box inputs. These scalers can be used to recover the number of trigger signals occurring on each of the source and trigger box inputs, besides the information coded for each event in the trigger register.
+The "D" connector of the trigger module is directly connected to first 16 inputs of a {{:wiki:Manual_LeCroy_Scaler_4434.pdf|32-channel scaler LeCroy 4434 module}} (see mapping of the inputs and outputs of the trigger module in section [[Trigger#Inputs and outputs|Inputs and outputs]]). Scalers are connected to each of the trigger source inputs, as well as trigger box inputs. These scalers can be used to recover the number of trigger signals occurring on each of the source and trigger box inputs, besides the information coded for each event in the trigger register.
-In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger.
+For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger.
 The remining 16 scaler input channels (pins 17 to 32 in module) are connected to an ECL-NIM-ECL converter fed by a 16-channel {{:wiki:MCFD-16.pdf|Mesytec CFD (MCFD-16)}}, which sends the signals from the S800 detectors (**E1 up,** **E1 down**, **CRDC1**, **CRDC2**, **OBJ_SCI**, **A1900 SCI**, and **OR Hodoscope**).

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